摘要：A gallium nitride(GaN)power amplifier monolithic microwave integrated circuit(MMIC)with a wide band and high efficiency in the microwave frequency band is proposed in this *** power amplifier MMIC uses a 0.15^im GaN high electron mo-bility transistor(HEMT)*** operating frequency band of the amplifier can cover the whole K-band,i.e.,17-26.5 GHz.

摘要：An analog baseband circuit of high linearity and high gain accuracy for a digital audio broadcasting receiver is implemented in a 0.18-μm rfCMOS *** circuit comprises a 3rd-order active-RC complex filter（CF） and a programmable gain amplifier（PGA）.An automatic tuning circuit is also designed to tune the CF＇s pass *** of the class-A fully differential operational amplifier（FDOPA） adopted in the conventional CF and PGA design,a class-AB FDOPA is specially employed in this circuit to achieve a higher linearity and gain accuracy for its large current swing capability with lower static current *** the PGA circuit,a novel DC offset cancellation technique based on the MOS resistor is introduced to reduce the settling time significantly.A reformative switching network is proposed,which can eliminate the switch resistor＇s influence on the gain accuracy of the *** measurement result shows the gain range of the circuit is 10-50 dB with a 1-dB step size,and the gain accuracy is less than ±0.3 *** OIP3 is 23.3 dBm at the gain of 10 *** results show that the settling time is reduced from 100 to 1 *** image band rejection is about 40 *** only draws 4.5 mA current from a 1.8 V supply voltage.

摘要：A limiting amplifier IC implemented in 65 nm CMOS technology and intended for high-speed optical fiber communications is described in this *** inductorless limiting amplifier incorporates5-stage 8 dB gain limiting cells with active feedback and negative Miller capacitance,a high speed output buffer with novel third order active feedback,and a high speed full-wave *** receiver signal strength indictor(RSSI) can detect input signal power with 33 dB dynamic range,and the limiting amplifier features a programmable loss of signal(LOS) indication with external *** sensitivity of the limiting amplifier is 5.5mV at BER = 10 ^(-12) and the layout area is only 0.53 ×0.72 mm because of no passive *** total gain is over 41 dB,and bandwidth exceeds12 GHz with 56 mW power dissipation.

摘要：A fully integrated low noise amplifier( LNA) for WLAN 802. 11 ac is presented in this article.A cascode topology combining BJT and MOS transistor is used for better performance. An inductive source degeneration is chosen to get 50 Ohm impedance matching at the input. The noise contribution of common gate transistor is analyzed for the first time. The designed LNA is verified with IBM silicon-germanium(SiGe ) 0. 13μm BiCMOS process. The measured results show that the designed LNA has the gain of 13 dB and NF of 2. 8 dB at the center frequency of 5. 5 GHz. The input reflection S11 and output reflection S22 are equal to-19 dB and-11 dB respectively. The P-1 dB and IIP3 are-8. 9 dBm and 6. 6 dBm for the linearity performance respectively. The power consumption is only 1. 3 mW under the 1. 2 V supply. LNA achieves high gain,low noise,and high linearity performance,allowing it to be used for the WLAN 802. 11 ac applications.

摘要：A low power VCO with a wide tuning range and low phase noise has been designed and realized in a standard 90 nm CMOS technology. A newly proposed current-reuse cross-connected pair is utilized as a negative conductance generator to compensate the energy loss of the resonator. The supply current is reduced by half compared to that of the conventional LC-VCO. An improved inversion-mode MOSFET（IMOS） varactor is introduced to extend the capacitance tuning range from 32.8% to 66%. A detailed analysis of the proposed varactor is provided. The VCO achieves a tuning range of 27–32.5 GHz, exhibiting a frequency tuning range（FTR） of 18.4%and a phase noise of –101.38 dBc/Hz at 1 MHz offset from a 30 GHz carrier, and shows an excellent FOM of –185dBc/Hz. With the voltage supply of 1.5 V, the core circuit of VCO draws only 2.1 m A DC current.

摘要：Phase locked loop(PLL) is a typical analog-digital mixed signal circuit and a method of conducting a top level system verification including PLL with standard digital simulator becomes especially *** behavioral level model(BLM) of the PLL in Verilog-HDL for pure digital simulator is innovated in this paper,and the design of PLL based clock and data recovery(CDR)circuit aided with jitter attenuation PLL for SerDes application is also *** CDR employs a dual-loop architecture where a frequency-locked loop acts as an acquisition aid to the phase-locked *** simultaneously meet jitter tolerance and jitter transfer specifications defined in G.8251 of optical transport network(ITU-T OTN),an additional jitter attenuation PLL is *** results show that the peak-to-peak jitter of the recovered clock and data is 5.17 ps and 2.3ps *** core of the whole chip consumes 72 mA current from a 1.0V supply.

摘要：A 0.5 V static master-slave D flip-flop （DFF） divider-by-2 is implemented with a 0.13 μm 1P8M rf- mixed signal CMOS process. Low-threshold transistors in a deep-N well with forward-body bias technology are used in the circuit. Each of the D-latch with source coupled logic consists of sensing and latching circuits. To increase the maximum operating frequency and decrease power consumption, the latching current is one half of the sensing current. The circuit optimization methods are described in this paper. The measured maximum operating frequency is 6.5 GHz and the minimum input singled-signal amplitude is 0.15 V.

摘要：This paper presents the design of an ultralow power receiver front-end designed for a wireless sensor network （WSN） in a 0.18 μm CMOS process. The author designs two front-ends working in the saturation region and the subthreshold region respectively. The front-ends contain a two-stage cross-coupling cascaded common-gate （CG） LNA and a quadrature Gilbert IQ mixer. The measured conversion gain is variable with high gain at 24 dB and low gain at 7 dB for the saturation one, and high gain at 22 dB and low gain at 5 dB for the subthreshold one. The noise figure （NF） at high gain mode is 5.1 dB and 6.3 dB for each. The input 1 dB compression point （IPldB） at low gain mode is about -6 dBm and -3 dBm for each. The front-ends consume about 2.1 mA current from 1.8 V power supply for the saturation one and 1.3 mA current for the subthreshold one. The measured results show that, comparing with the power consumption saving, it is worth making sacrifices on the performance for using the subthreshold technology.

摘要：This paper presents a low noise amplifier（LNA）,which could work at an ultra-low voltage of 0.5 V and was optimized for WSN application using 0.13μm rf-CMOS *** circuit was analyzed and a new optimization method for a folded cascode LNA was *** results of the proposed circuit demonstrated a power gain of 14.13 dB,consuming 3 mW DC power,showing 1.96 dB NF and an input 1-dB compression point of -19.9 *** input power matching（S_（11）） and output power matching（S_（22）） were below -10 *** results indicate that this LNA is fully applicable to low voltage and low power applications.

摘要：This paper presents a differential low power low noise amplifier designed for the wireless sensor network （WSN） in a TSMC 0.18μm rf CMOS process.A two-stage cross-coupling cascaded common-gate（CG） topology has been designed as the *** first stage is a capacitive cross-coupling *** can reduce the power and noise *** second stage is a positive feedback cross-coupling topology,used to set up a negative resistance to enhance the equivalent Q factor of the inductor at the load to improve the gain of the LNA.A differential inductor has been designed as the load to achieve reasonable *** inductor has been simulated by the means of momentum electromagnetic simulation in ADS.A ＂double-π＂ circuit model has been built as the inductor model by iteration in *** inductor has been fabricated separately to verify the model. The LNA has been fabricated and *** LNA works well centered at 2.44 *** measured gain S_（21） is variable with high gain at 16.8 dB and low gain at 1 *** NF（noise figure） at high gain mode is 3.6 dB,the input referenced 1 dB compression point（IP1dB） is about -8 dBm and the IIP3 is 2 dBm at low gain *** LNA consumes about 1.2 mA current from 1.8 V power supply.