摘要：Due to the importance of metal layers in the product yield,serpentine test structures are usually fabricated on test chips to extract parameters for yield *** this paper,the confidence level and estimation precision of the average defect density on metal layers are investigated to minimize the randomness of experimental results and make the measured parameters more *** the basis of the Poisson yield model,the method to determine the total area of all serpentine test structures is obtained using the law of large numbers and the Lindeberg-Levy ***,the method to determine an adequate area of each serpentine test structure is proposed under a specific requirement of confidence level and estimation *** results of Monte Carlo simulation show that the proposed method is consistent with theoretical *** is also revealed by wafer experimental results that the method of designing serpentine test structure proposed in this paper has better performance.

摘要：We present a semi-custom design methodology based on transistor tuning to optimize the design performance. Compared with other transistor tuning approaches, our tuning process takes the cross-talk effect into account and prominently reduces the complexity for circuit simulation and analysis by decomposing the circuit network utilizing graph theory. Furthermore, the incremental placement and routing for the corresponding transistor tuning in conventional approaches is not required in our methodology, which might induce timing graph variation and additional iterations for design convergence. This methodology combines the flexible automated circuit tuning and physical design tools to provide more opportunities for design optimization throughout the design cycle.

摘要：For accurate prediction of via yield, via chains are usually fabricated on test chips to investigate issues about vias. To minimize the randomness of experiments and make the testing results more convincing, the confidence level and estimation precision of the via failure rate are investigated in this paper. Based on the Poisson yield model, the method of determining an adequate number of total vias is obtained using the law of large numbers and the de Moivre-Laplace theorem. Moreover, for a specific confidence level and estimation precision, the method of determining a suitable via chain length is proposed. For area minimization, an optimal combination of total vias and via chain length is further determined. Monte Carlo simulation results show that the method is in good accordance with theoretical analyses. Results of via failure rates measured on test chips also reveal that via chains designed using the proposed method has a better performance. In addition, the proposed methodology can be extended to investigate statistical significance for other failure modes.

摘要：DFM (design-for-manufacturability) method, which aims to improve manufacturability of ICs through specific design considerations, is becoming important nowadays. In particular, standard cells now should be designed by DFM method. This paper reports a DFM flow for sub-100 nm standard cell design with a group of technologies for process modeling, manufacturability simulation and trial RETs. Based on this flow, a set of DFM-friendly 90m standard cells were designed.

摘要：A wideband fractional-N frequency synthesizer is implemented in a 65 nm CMOS *** employs a wideband LC voltage-controlled oscillator（VCO） with optimized VCO gain（KVCO/and a sub-band step to improve automatic frequency calibration（AFC） efficiency at negligible expense of phase noise *** agile AFC is realized by direct mapping based on the division ratio,and optional redundant counting and comparing calibration is introduced accommodating PVT variations,which samples the reference clock using the prescaled VCO output as a discriminating clock.A charge pump with switched charging current is adopted to compensate for the loop bandwidth *** results show this directly-mapped AFC locates the target sub-band in 100 ns and only needs 1.2 s for redundant *** frequency synthesizer spans a frequency range from 0.62 to 1.52 GHz,with phase noise of-86 dBc/Hz at 10 kHz offset and-122 dBc/Hz at 1 MHz offset while consuming 9.76 mA from a 1.2 V supply.

摘要：Collision and security issues are considered as barriers to RFID *** this paper,a parallelizable anti-collision based on chaotic sequence combined dynamic frame slotted aloha to build a high-efficiency RFID system is *** the tags parallelizable identification,we design a Discrete Markov process to analyze the success identification *** a mutual authentication security protocol merging chaotic anti-collision is *** theoretical analysis and simulation results show that the proposed identification scheme has less than 45.1%of the identification time slots compared with the OVSF-system when the length of the chaos sequence is *** success identification rate of the proposed chaotic anti-collision can achieve 63%when the number of the tag *** test the energy consumption of the presented authentication protocol,which can simultaneously solve the anti-collision and security of the UHF RFID system.

摘要：研究目的:性能估计已成为异构MPSo C设计中一个非常重要且具有挑战性的任务。在设计早期进行准确快速估计性能对于设计空间探索十分必要。本文采用GCC剖析技术和代码标注技术,结合MPSo C分层抽象概念,探讨逐层次完善的性能评估技术在MPSo C体系结构探索中的应用。创新要点:为面向多媒体应用的MPSo C性能估计提出一个从VA层到TA层的剖析和标注相结合流程,使性能估计可以被有效逐层完善。研究方法:基于GNU gcov工具,在本机模拟过程中剖析给定应用程序代码执行的统计信息,并且支持实时性能分析,快速、准确估计VA模型的计算负载。基于VA模型得到的计算负载性能的结果标注,利用TA模型的System C时序精确级仿真得到通信延时结果,使TA模型性能估计更高效,完善整个MPSo C性能估计。重要结论:研究一个剖析和标注技术相结合的MPSo C性能评估方法和流程。在VA层得到准确计算负载性能并标注给TA层;在TA层利用基于标注的仿真方法完善通信延时,使得性能估计更高效。通过M-JPEG和MEPG2两个典型视频多媒体应用实验,展示本文方法的高效、快速与准确。

摘要：A novel loss compensation technique for a series-shunt single-pole double-throw （SPDT） switch is pre- sented operating in the 60 GHz. The feed-forward compensation network which is composed of an NMOS, a couple capacitance and a shunt inductance can reduce the impact of the feed forward capacitance to reduce the insertion loss and improve the isolation of the SPDT switch. The measured insertion loss and isolation characteristics of the switch somewhat deviating from the 60 GHz are analyzed revealing that the inaccuracy of the MOS model can greatly degrade the performance of the switch. The switch is implemented in TSMC 90-nm CMOS process and exhibits an isolation of above 27 dB at transmitter mode, and the insertion loss of 1.8-3 dB at 30--65 GHz by layout simulation. The measured insertion loss is 2.45 dB at 52 GHz and keeps 〈 4 dB at 30-64 GHz. The measured isolation is better than 25 dB at 30--64 GHz and the measured return loss is better than 10 dB at 30-65 GHz. A measured input 1 dB gain compression point of the switch is 13 dBm at 52 GHz and 15 dBm at 60 GHz. The simulated switching speed with rise time and fall time are 720 and 520 ps, respectively. The active chip size of the proposed switch is 0.5 × 0.95 mm2.