摘要：A 32-bit pipeline accumulator with carry ripple topology is implemented for direct digital frequency *** increase the throughout while hold down the area and power consumption,a method to reduce the number of the pre-skewing registers is *** number is reduced to 29% of a conventional pipeline *** propagation delay versus bias current of the adder circuit with different size transistors is *** analyze the delay by employing the open circuit time constant *** to the simulation results,the maximum error is less than 8%.A method to optimum the design of the adder based on the propagation delay is *** clock traces for the 32-bit adder are heavily loaded,as there are 40 registers being connected to ***,the differential clock traces,which are much longer than the critical length,should be treated as transmission *** a clock distribution method and a termination scheme are proposed to get high quality and low skew clock signals.A multiple-type termination scheme is proposed to match the transmission line *** 32-bit accumulator was measured to work functionally at 5.3 GHz.