摘要：A novel clock structure of a low-power 16-bit very large instruction word (VLIW) digital signal processor (DSP) was proposed. To improve deterministic clock gating and to solve the drawback of conventional clock gating circuit in high speed circuit, a distributed and early clock gating method was developed on its instruction fetch & decoder unit, its pipelined data-path unit and its super-Harvard memory interface unit. The core was implemented following the Synopsys back-end flow under TSMC (Taiwan Silicon manufacture corporation) 0.18-μm 1.8-V 1P6M process, with a core size of 2 mm×2 mm. Result shows that it can run under 200 MHz with a power performance around 0.3 mW/MIPS. Meanwhile, only 39.7% circuit is active simultaneously in average, compared to its non-gating counterparts.

摘要：Numerous Internet security incidents have shown that support from secure operating systems is paramount to fighting threats posed by modern computing environments. Based on the requirements of the relevant national and international standards and criteria, in combination with our experience in the design and development of the ANSHENG v4.0 secure operating system with high security level （hereafter simply referred to as ANSHENG OS）, this paper addresses the following key issues in the design of secure operating systems with high security levels： security architecture, security policy models, and covert channel analysis. The design principles of security architecture and three basic security models： confidentiality, integrity, and privilege control models are discussed, respectively. Three novel security models and new security architecture are proposed. The prominent features of these proposals, as well as their applications to the ANSHENG OS, are elaborated. Cover channel analysis （CCA） is a well-known hard problem in the design of secure operating systems with high security levels since to date it lacks a sound theoretical basis and systematic analysis approach. In order to resolve the fundamental difficulties of CCA, we have set up a sound theoretical basis for completeness of covert channel identification and have proposed a unified framework for covert channel identification and an efficient backward tracking search method. The successful application of our new proposals to the ANSHENG OS has shown that it can help ease and speedup the entire CCA process.

摘要：Based on a stochastic wire length distributed model, the interconnect distribution of a three-dimensional integrated circuit （3D IC） is predicted exactly. Using the results of this model, a global interconnect design window for a giga-scale system-on-chip （SOC） is established by evaluating the constraints of 1） wiring resource, 2） wiring bandwidth, and 3） wiring noise. In comparison to a two-dimensional integrated circuit （2D IC） in a 130-nm and 45-nm technology node, the design window expands for a 3D IC to improve the design reliability and system performance, further supporting 3D IC application in future integrated circuit design.

摘要：This paper proposes an asynchronous complex pipeline based on ARM-V3 instruction set. Muller pipeline structure is used as prototype, and the factors which may affect pipeline performance are analyzed. To balance the difficulty of asynchronous design and performance analysis, both complete asynchronous and partial asynchronous structures aere designed and compared. Results of comparison with the well-Rnown industrial product ARM922T verify that about 30% and 40% performance improvement of the partiM and complete asynchronous complex pipelines can be obtained respectively. The design methodologies can also be used in the design of other asynchronous pipelines.

摘要：A novel anti-jamming integrated CMOS current-sensing circuit for current-mode buck regulators is presented. Based on the widely-used traditional current-sensing structure, anti-jamming performance is improved significantly by adding on-chip capacitors and one-shot circuit. Also the transient response is faster through the introduction of current offset. The circuit is concise, simple to implement and suits for SoC applications with single power supply. A dualoutput current-mode DC-DC buck converter with proposed structure has been fabricated with a 0.5 μm CMOS process for validation. In the 2.5–5.5 V input range, the two channels work steadily in the load current range of 0–600 mA. And the measured maximum efficiency is up to 96%.

摘要：A 19 mW highly integrated GPS receiver with a ΣΔ fractional-N synthesizer is presented in this ***-N frequency synthesizer architecture was adopted in this work, to provide more degrees of freedom in the synthesizer design.A high linearity low noise amplifier(LNA) is integrated into the *** radio receiver chip was fabricated in a 0.18 μm complementary metal oxide semiconductor(CMOS) process and packaged in a 48-pin 2 mm×2 mm land grid array chip scale *** chip consumes 19 mW(LNA1 excluded) and the LNA1 6.3 *** performances are:noise figure36 dB, and-108 dBc/Hz @ 1 MHz phase noise offset from the *** carrier noise ratio(C/N) can reach 41 dB at an input power of-130 *** chip operates over a temperature range of-40, 120 °C and ±5% tolerance over the CMOS technology process.

摘要：GaAs-based planar Gunn diodes with A1GaAs hot electron injector have been successfully developed to be used as a local oscillator of 76 GHz in monolithic millimeter-wave integrated circuits. We designed two kinds of structure diode, one has a fixed distance between the anode and cathode, but has variational cathode area, the other has a fixed cathode area, but has different distances between two electrodes. The fabrication of Gunn diode is performed in accordance with the order of operations： cathode defining, mesa etching, anode defining, isolation, passivation, via hole and electroplating. A peak current density of 29.5 kA/cm^2 is obtained. And the charavteristics of negative differential resistance and the asymmetry of the current-voltage curve due to the A1GaAs hot electron injector are discussed in detail. It is demonstrated that the smaller size of active area corresponds to the smaller current, and the shorter distance between anode and cathode also corresponds to the lower threshold voltage and higher peak current, and hot electron injector can effectively enhance the radio frequency conversion efficiency and output power.

摘要：Through-silicon-via （TSV） to TSV crosstalk noise is one of the key factors affecting the signal integrity of three- dimensional integrated circuits （3D ICs）. Based on the frequency dependent equivalent electrical parameters for the TSV channel, an analytical crosstalk noise model is established to capture the TSV induced crosstalk noise. The impact of various design parameters including insulation dielectric, via pitch, via height, silicon conductivity, and terminal impedance on the crosstalk noise is analyzed with the proposed model. Two approaches are proposed to alleviate the TSV noise, namely, driver sizing and via shielding, and the SPICE results show 241 rnV and 379 mV reductions in the peak noise voltage, respectively.

摘要：This paper presents a novel high-speed low voltage differential signaling （LVDS） driver design for pointto-point communication. The switching noise of the driver was greatly suppressed by adding a charge/discharge circuit and the operating frequency of the circuit was also increased. A simple and effective common-mode feedback circuit was added to stabilize the output common-mode voltage. The proposed driver was implemented in a standard 0.35 μm CMOS process with a die area of 0.15 mm^2. The test result shows that the proposed driver works well at 2.2 Gbps with power consumption of only 23 mW and 21.35 ps peak-to-peak jitter under a 1.8 V power supply.

摘要：A voltage-controlled oscillator（VCO） with dual stages of accumulation mode varactors for a multimode global navigation satellite system（GNSS） application,which adopts sigma-delta fractional-N technology in the synthesizer,is *** structure is selected to optimize the frequency coverage and tuning linearity, based on a general analysis of the parasitic capacitance in the coarse tuning switch bank cells,which cover the global positioning system（GPS） and Beidou（BD） *** VCO implemented in the 0.18μm CMOS process can cover the GPS L1,BD B1,B2 and B3 bands with sufficient margin,and exhibits low phase noise by using this tuning curve linearization *** equalized K_（vco）,characteristic behavior further offers a wide voltage tuning range and improves the stability of the closed loop.