摘要：The circuit testable realization and its fault detection for logic functions with ESOP (EXOR-Sum-Of-Products) expressions are studied. First of all, for the testable realization by using XOR gate cascade, a test set with 2 n + m+ 1vectors for the detections of AND bridging faults and a test set with 2n + mvectors for the detections of OR bridging faults are presented. Secondly, for the testable realization by using XOR gate tree, a test set with 2n + mvectors for the detections of AND bridging faults and a test set with 3n + m+ 1vectors for the detections of OR bridging faults are presented. Finally, a single fault test set with n + 5vectors for the XOR gate tree realization is pre- sented. Where n is the number of input variables and m is the number of product terms in a logic function.

摘要：The circuit testable realizations of multiple-valued functions are studied in this letter. First of all,it is shown that one vector detects all skew faults in multiplication modulo circuits or in addi-tion modulo circuits,and n+1 vectors detect all skew faults in the circuit realization of multiple-valued functions with n inputs. Secondly,min(max) bridging fault test sets with n+2 vectors are pre-sented for the circuit realizations of multiple-valued logic functions. Finally,a tree structure is used instead of cascade structure to reduce the delay in the circuit realization,it is shown that three vec-tors are sufficient to detect all single stuck-at faults in the tree structure realization of multiple-valued logic functions.