摘要：Quantum-dot cellular automata （QCA） is an emerging area of research in reversible computing. It can be used to design nanoscale circuits. In nanocommunication, the detection and correction of errors in a received message is a major factor. Besides, device density and power dissipation are the key issues in the nanocommunication architecture. For the first time, QCA-based designs of the reversible low-power odd parity generator and odd parity checker using the Feynman gate have been achieved in this study. Using the proposed parity generator and parity checker circuit, a nanocommunication architecture is pro- posed. The detection of errors in the received message during transmission is also explored. The proposed QCA Feynman gate outshines the existing ones in terms of area, cell count, and delay. The quantum costs of the proposed conventional reversible circuits and their QCA layouts are calculated and compared, which establishes that the proposed QCA circuits have very low quantum cost compared to conventional designs. The energy dissipation by the layouts is estimated, which ensures the possibility ofQCA nano-device serving as an alternative platform for the implementation of reversible circuits. The stability of the proposed circuits under thermal randomness is analyzed, showing the operational efficiency of the circuits. The simulation results of the proposed design are tested with theoretical values, showing the accuracy of the circuits. The proposed circuits can be used to design more complex low-power nanoscale lossless cation architecture such as nano-transmitters and nano-receivers

摘要：With the rapid development of network technologies, it is necessary to make use of an aided tool (AT) to help enterprise network design (END). The AT must process many requirements qualitatively and quantitatively and then give out the logical network guidance and preferred solution. The AT also needs to carry out a simulation program, and gives the feasibility report. This paper will introduce the authors research work on above aspects.

摘要：A novel nanoscale MOSFET with a source/drain-to-gate non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first *** gate leakage behaviour of the novel MOSFET structure has been investigated with the help of a compact analytical model and Sentaurus simulation. A fringing gate electric field through the dielectric spacer induces an inversion layer in the non-overlap region to act as an extended S/D（source/drain） *** is found that an optimal source/drain-to-gate non-overlapped and high-A：spacer structure has reduced the gate leakage current to a great extent as compared to those of an overlapped ***,the proposed structure had improved off current,subthreshold slope and drain induced barrier lowering（DIBL） *** is concluded that this structure solves the problem of high leakage current without introducing extra series resistance.

摘要：A non-slicing approach, Corner Block List (CBL), has been presented *** CBL only can represent floorplans without empty rooms, the algorithm based on CBLcannot get the optimum placement. In this paper, an extended corner block list, ECBLλ, isproposed. It can represent non-slicing floorplan including empty rooms. Based on the optimumsolution theorem of BSG (bounded-sliceline grid), it is proved that the solution space of ECBLn,where n is the number of blocks, contains the optimum block placement with the minimum area.A placement algorithm based on ECBLλ, whose solution space can be controlled by setting λ,the extending ratio, is completed. When λ is set as n, the algorithm based on ECBLn is theoptimum placement search algorithm. Experiments show that λ has a reasonable constant rangefor building block layout problem, so the algorithm can translate an ECBLλ representation toits corresponding placement in O(n) time. Experimental results on MCNC benchmarks showpromising performance with 7% improvement in wire length and 2% decrease in dead space overalgorithms based on CBL. Meanwhile, compared with other algorithms, the proposed algorithmcan get better results with less runtime.

摘要：Many websites use verification codes to prevent users from using the machine automatically to register,login,malicious vote or irrigate but it brought great burden to the enterprises involved in internet marketing as entering the verification code *** the verification code security system needs the identification method as the corresponding testing *** propose an anisotropic heat kernel equation group which can generate a heat source scale space during the kernel evolution based on infinite heat source axiom,design a multi-step anisotropic verification code identification algorithm which includes core procedure of building anisotropic heat kernel,settingwave energy information parameters,combing outverification codccharacters and corresponding peripheral procedure of gray scaling,binarizing,denoising,normalizing,segmenting and identifying,give out the detail criterion and parameter *** test show the anisotropic heat kernel identification algorithm can be used on many kinds of verification code including text characters,mathematical,Chinese,voice,3D,programming,video,advertising,it has a higher rate of 25%and 50%than neural network and context matching algorithm separately for Yahoo site,49%and 60%for Captcha site,20%and 52%for Baidu site,60%and 65%for 3DTakers site,40%,and 51%.for MDP site.

摘要：Role based access control is one of the widely used access control *** are investigations in the literature that use knowledge representation mechanisms such as formal concept analysis(FCA),description logics,and Ontology for representing access control ***,while using FCA,investigations reported in the literature so far work on the logic that transforms the three dimensional access control matrix into dyadic formal *** transformation is mainly to derive the formal concepts,lattice structure and implications to represent role hierarchy and constraints of *** this work,we propose a methodology that models RBAC using triadic FCA without transforming the triadic access control matrix into dyadic formal *** discussion is on two lines of *** present how triadic FCA can provide a suitable representation of RBAC policy and we demonstrate how this representation follows role hierarchy and constraints of RBAC on sample healthcare network available in the literature.

摘要：We consider the problem of learning a representation of both spatial relations and dependencies between objects for indoor scene *** propose a novel knowledge graph framework based on the entity-relation model for representation of facts in indoor scene design, and further develop a weaklysupervised algorithm for extracting the knowledge graph representation from a small dataset using both structure and parameter learning. The proposed framework is flexible, transferable, and readable. We present a variety of computer-aided indoor scene design applications using this representation, to show the usefulness and robustness of the proposed framework.

摘要：The use of communication networks in control loops has gained increasing attention in recent years due to its advantages and flexible applications. The network quality-of-service （QoS） in those socalled networked control systems always fluctuates due to changes of the traffic load and available network resources, This paper presents an intelligent scheduling controller design approach for a class of NCSs to handle network QoS variations, The sampling period and control parameters in the controller are simultaneously scheduled to compensate for the network QoS variations. The estimation of distribution algorithm is used to optimize the sampling period and control parameters for better performance. Compared with existing networked control methods, the controller has better ability to compensate for the network QoS variations and to balance network loads. Simulation results show that the plant setting time with the intelligent scheduling controller is reduced by about 64.0% for the medium network load and 49.1% for high network load and demonstrate the effectiveness of the proposed approaches.

摘要：A Weighted Essentially Non-Oscillatory scheme(WENO) is a solution to hyperbolic conservation laws,suitable for solving high-density fluid interface instability with strong intermittency. These problems have a large and complex flow structure. To fully utilize the computing power of High Performance Computing(HPC) systems, it is necessary to develop specific methodologies to optimize the performance of applications based on the particular system’s architecture. The Sunway TaihuLight supercomputer is currently ranked as the fastest supercomputer in the world. This article presents a heterogeneous parallel algorithm design and performance optimization of a high-order WENO on Sunway TaihuLight. We analyzed characteristics of kernel functions, and proposed an appropriate heterogeneous parallel model. We also figured out the best division strategy for computing tasks,and implemented the parallel algorithm on Sunway TaihuLight. By using access optimization, data dependency elimination, and vectorization optimization, our parallel algorithm can achieve up to 172× speedup on one single node, and additional 58× speedup on 64 nodes, with nearly linear scalability.

摘要：Hierarchical art was used to solve the mixed mode placement for three dimensional （3-D） integrated circuit design. The 3-D placement flow stream includes hierarchical clustering, hierarchical 3-D floorplanning, vertical via mapping, and recursive two dimensional （2-D） global/detailed placement phases. With state-of-the-art clustering and de-clustering phases, the design complexity was reduced to enhance the placement algorithm efficiency and capacity. The 3-D floorplanning phase solved the layer assignment problem and controlled the number of vertical vias. The vertical via mapping transformed the 3-D placement problem to a set of 2-D placement sub-problems, which not only simplifies the original 3-D placement problem, but also generates the vertical via assignment solution for the routing phase. The design optimizes both the wire length and the thermal load in the floorplan and placement phases to improve the performance and reliability of 3-D integrate circuits. Experiments on IBM benchmarks show that the total wire length is reduced from 15% to 35% relative to 2-D placement with two to four stacked layers, with the number of vertical vias minimized to satisfy a pre-defined upper bound constraint. The maximum temperature is reduced by 16% with two-stage optimization on four stacked layers.